More Complex parts of Computational Redstone E.G: Caches / serial memory and pipline

General
21

? if it cant store instructions how come he used it as a ROM

22

did he just use the data like instructions or smth?

23

you are free to use it as ROM for the time being. allows later use to add things like a storage unit. Its all context and what kind of model the memory/storage is shown to the programmer.

24

also along with that is the instruction Icache swap nessisary if you have one and if so what are the oprands

25

cache in its true form does not need you to micro manage it. what you suggest is more along the lines of a paged memory/memory banking

26

so its only needed for manual cache systems or paged memory that dear Eithanz hates so much xc

27

so how do auto stuff work and how do not auto stuff work

28

and along with that what other instructions might be good for 5bit opcode cos i got 20 rn

29

cache is 2 components: It stores data and stores the data about that data, so the address, valid bits, etc. You give cache the full address and it itself checks it against what it is currently holding. if theres a hit, no problem. if theres a miss, it has to swap it out. the complexity of the hardware comes from the layout of the cache (set & way associativity), eviction algorithms (Least Recently Used, random, etc) and cache coherency protocols which allows for multi-core setups. If you ask about any of these, a video explains it better.

30

:skull: i heard cache coherency is a bitch

31

so which is easier?

32

obviously, paged memory is easier and more predictable to the programmer. downside is that any code has to be tailored to the memory architecture of that cpu. its fine if like to make code specifically for that setup and don’t change it after.

33

so would you need ICS every few instructions if using paged mem
and how does it work?

34

this is really helpful btw ty

35

speaking of which can you also tell me the oprands for a ICS instructions

36

all those questions are dependend on the architecture. how big are your pages? how many instructions fit in a page? how many pages can you hold in the memory close by? ICS requires the page address and the place you want to store into. The rest is the wild west.

37

Oh i im planning to use 64b or 32byte Paged mem that can either hold 32instrucitons or 16
it is also Harvard arch and has a 512byte/256instructions memory storage for the cpu

38

hex storage for better density

39

i feel like using the bottom version (hex ram) as it honestly just feels better idk y

40

for the ICS oprands i just wrote Cache line, page,offset