What’s a thing you have made which demonstrates sufficient engineering knowledge?: 3 stage pipelined CPU
What engineering work went into designing this device?:
When Engineer rank was first introduced, I thought i had to rank up to be one of the first ones to get it. I didnt have a good enough CPU I could aplly with, so i started a new project. I spent almost a year trying to get this CPU done, cause every component it has, was created by me (if you dont count the registers and the cca), and i had to make it pipelined (it started by not beeing piped). On top of that, URCL came up and I got super busy, and changed some parts of it to make it more compatible with it.
After all of this time i can finally present to you and aplly to engineer with KORE (name of the CPU, that isn’t done at the time of this post).
FEATURES:
3 stages (fetch; decode; execute/writeback)
8-bit ALU with Cin !A !B FC RSH LSH
8 general purpose registers
Accumulator architechture design
3 flags: Zero; MSB, Carry (underflow/overflow)
96 bytes of program memory
16 bytes of RAM
8 bytes of Call stack memory
Can handle multi word instructions such as loading Immediate values or Conditional Branching
Looks really nice, pls post speed and, also, very important, please give an ISA spreadsheet of some sort.
Basically what somebody would need to produce programs for it.
This cpu was suposed to be my first vertical big project, and I wanted start simple, but as i said, it suffered many changes throughout the year. Pointers are something I didnt plan on support, and til this day I dont. About the opcode capacity: This CPU fits on 64x64 area. I could have more decoders for more operations, or even add more support for pointers, I/O (smt I dont support) and other stuff like boolean ops. On KORE 2.0 ill add a lot more stuff and Ill restructure the entire CPU so I can start having these essencial components with no restrictions. Also clock speed is 10 ticks, but i never tried overclocking it and i doubt it will work. you can have slower clock speeds tho.
