Minecraft name:
SAN_guan What’s a thing you have made which demonstrates sufficient engineering knowledge?:
me made a cpu
brief introduction:
this is a cpu with 4 stage pipeline and the four stage is fetch , decode , execute and writeback
have 16 regesters for alu to use (its 32 regsters but a and b regsters use the same write address )
use 16 bit command to run (4bit is opcode , 4bit is writeback address ,other 8bit is imm and read address)
have 8 i/o part (use 4bit addr so can extend more than 8 )
up to 127 command for prom (7bit address)
the ram have 64 spaces for cpu to use
some features it have:
can do (add sub ani adi and xor or ) some easy math and logic operation
it have the forwarding so can solve the data hazard problem
have 4 bit branch flag (lsb , msb , zero , cin) for command to use
can use pointer to jump What engineering work went into designing this device?:
it was a bold attempt to break away from some of my previous cpu designs
when me start build it me want :
1 this cpu need use four stage pipeline to work
2 the cpu clock need less than 30 ticks
3 need have the i/o part and can use command to control
4 use 16bit length for instruction
5 have forwarding feature
this cpu have more fast clock cycle (my designed the cpu earlier need very long clock cycle because they are single-cycle cpu)
I consulted a lot of books about how a pipeline cpu works, asked my school computer technology teacher for more useful knowledge, and my friends from ORE also recommended me some very well-designed cpus for me to learn how it work
in fact this cpu is the second version for me build
when i finish the first one and try to run some program it crush because my program have data hazard
so me add 2 mux for alu 2 input and use the write address and read address to decide next data will from where
my instruction just have 16 bit so cant use instruction direct to control the ram because ram have 7 bit address and opcode have 4 bits the remaining 5bit maybe not enough to support some of my operations , so i use 2 regesters help me indirect use the ram , one register give ram write/read address and one register give ram data or store data from ram output
the biggest challenge for me is to solve the data hazard and ram problem so i think this 2 are the biggest engineering and challenges in this cpu
Correct me if I’m wrong, but you aren’t a builder yet, so you have to apply there first. (sorry if I’m wrong, I’m basing this off the fact that you haven’t posted yet lol)
im so sorry for taking so long to reply you. these time im busy with my new cpu because me think this 1 is not the best i can make. i will post a new applycation under this post.
and answer ur question
1 this cpu (old one) clock speed is 25tick
2 it can run the bouncing_ball and some easy program
sorry! its my problem to take so long time to reply you. im busy with my new cpu these time because me think now this 1 is not the best. i will send a new applycation under this post.
answer your question
1 the cpu clock speed is 25tick
2 the ISA is here (i forget upload ISA)
3 up to now this cpu just can run bouncing_ball and other easy program(thats why me want build a new better cpu)
this video have lot of important information about me new cpu.
and if know other thing about it can send post under post
me use longtime make video and put the cpu introduce and work video here
The ISA looks decent. Given that you are stating the clockspeed is 25 ticks, I assume the CPU does not have an instruction pipeline.
About the new CPU: I don’t speak chinese and neither do most members afaik.
As you claim 1 Hz, does that new CPU have a 10 (Redstone-) Tick clock?
Does it use pipelining?
Is the ISA the same, or did you add features like
-Branch prediction of some sort
-A way of calling functions (via callstack, or jumping to a location specified in accessible memory)
If it does have a pipeline, how many stages is it and what does each stage do?
that old cpu have 4 stage pipeline but me not assign each unit work well so it use long clock cycle time ,im not very happy with this cpu so come build a new cpu who happy with it.
answer your question about the new cpu ：
1 yes it have 10t clock.
2 yes it use the pipeline with 3 stage.
3 isa is not same me add more instruction like (bsh,lpc,brc…) in new cpu isa.
4 3 pipeline stage is (fetch,decode,execute/writeback) execute and writeback run in the same clock stage.
generally, most don’t really consider writeback to be a stage as it is mostly a write with a delay. Not that it matters much.
Also, in response to trecar, you have to be mindful about how your branch interacts with your cpu. As a general note, hardware solutions give you more points than software solutions. Don’t be afraid to ask. most think too hard about a solution that is already common among most builders.
