Just curious but i checked with some people but rzecz somehow said that fetch decode execute is 5stage pipeline because its FDDEW but im confused cos i learnt that that is still 4stage?
You can make one step be multiple stages - FDDEW is Fetch, Decode I, Decode II, Execute, Writeback
oh xd
generally, the write mentioned is the end of the execute stage (as end of stages are marked by latches/registers) so a writeback stage there would be trivial (think accumulator). however, if the write is delayed like on the mips architecture, halfway within the stage, it is its own stage.
Also there is no limit to what stages you have or how many you have of them. theres no predefined setup. its all personal preference.
ok i think i get it now
speaking of which i checked with some pros and they say your cpu must be fast to have 3stage pipeline
superpipelining mentioned
xdxd stevy
yo chat is mandelbrot set possible in 256 instructions?
Probably worth specifying which instructions you have
2 month later? F
name me one instruction that will be very good for mandelbrot
like an extra instruction
| No operation | NOP | |
|---|---|---|
| Halt | HLT | |
| Load Immediate | LDI | |
| Addition | ADD | |
| Subtraction | SUB | |
| AND bitwise | AND | |
| NOR bitwise | NOR | |
| XOR bitwise | XOR | |
| OR bitwise | OR | |
| Right Shift | RSH | |
| Memory load | MLD | |
| Memory Store | MSTR | |
| Jump | JMP | |
| Branch | BRH | |
| Port Load | PLD | |
| Port Store | PSTR |
i can change OR instruction into smth else
what do you suggest? if i want to run mandelbrot for example
Who are I talking to lmao?
??? wdym who are āIā talking about
but anyways i hope you can help me decide on my question
Sorry typo, I meant who r you talking to?
wait i didnt even see this but this is at the same time really wholesome and also incredibly true (thats right its shameless self promotion time)
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