Spry's nice application

Engineer Applications Aged
1

Minecraft name: b3nt1_xdxd (No, I don’t believe it either) , QSpry, SpryQBD, Spry0, SpryNebula, NebulaS1pry, rosneb, _Nebula__, SpryNebula53598

What’s a thing you have made which demonstrates sufficient engineering knowledge?:

NPPU3, pipelined minecraft processor /warp dasNPPU

image
image535×114 13.3 KB

Specs-

4 tick ALU, 7 dual read general purpose registers (virtual zero register), 5 stage pipeline (fetch, decode, execute, memory, writeback, ), 128 lines of program memory, 64 byte data memory,

13 ticks per clock cycle (0.83hz)

What engineering work went into designing this device?: I was always inspired by all of the server’s engineers, who encouraged me to keep trying and tought me (through their applications) that no matter how badly they failed, they kept rebuilding and redesigning.

*This CPU was inspired by rzecz, sammyuri and Tuchi_. so much thanks to them for inspiring me in computational redstone*

I began to design the first version of the CPU, beginning with the 4 tick ALU (credit to firetner) and dual read registers. Then made a 3 bit control ROM capable of executing just 7 different instructions. For a while I lost interest in making the CPU and decided to quit and I would never apply to get engineer. I wanted this to be better than my 2 previous family members of NPPU (NPPU and GPR POD), which only had small amounts of instructions and no pipelines, and that didn’t really happen. But then I came back a month later ready to redesign the computer entirely. I kept with a 4 tick ALU and 7 general purpose registers, but redesigned the control ROM to 5 bits, much more capable at a maximum of 32 executable instructions. Then I designed the pipeline registers, program ROM with 128 lines and a RAM device of 64 bytes. Several of my parts were flawed, like I coudln’t easily get output from the ALU, and it was hard to input to it as well. I had to fix all of these, which was very annoying. I finally started creating an instruction set architechture. At that point, I had really acheived my goal of far exceeding NPPU and GPR Pod. (Exceeding them more than those computers could ever wish to be :stuck_out_tongue:)

Image/s and/or video/s of the device:

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image1916×1042 392 KB

image
image1907×1037 231 KB

1 Like
2

i thiknk benti is Qsprite not too sure though

3

Please don’t post on other people’s applications!

4

Actually posting on applications is more acceptable on Engineer apps, just be sure to keep it on topic rather than silly stuff and you’re good

5

yes this is my application

6

it’s kind of confusing because of all of my usernames, but I made this

7

all of the usernames are there because those are all of my past usernames

8

Q… Sprite???

9

would it be possible to attach the ISA? if its online i’d love a link attached in the post/comment to look at it and if its ingame a picture would be nice
also if its on ORE a warp or coords would be greatly appreciated :pray:

1 Like
10

warp is dasNPPU

11

Reviewing some of the chat regarding your CPU and application, it sounds like you’ve only tested the ISA in an emulator and don’t necessarily have a functional CPU. Is this accurate?

Generally we require you to be finished with your project before submitting the application, not just prior to an interview. It wouldn’t make much sense to accept an application if we don’t know if you’ll manage to provide the required functional build.

12

yeah I’m working on making the CPU functional and it’ll be ready in maybe a day or 2, sorry for the inconvenience

13

do you have an isa?

1 Like
14

I’m also a little confused atm? Is your CPU rocking a 13 tick clock or a 0.83 Hz (12 tick) clock?

15

I’ve had a look and I just want to be completely honest - I personally would not approve this CPU for Engineer, even if it was functional.

I believe the quality of the build is subpar compared to current high-spec redstone CPU standards, and given this is an Engineer application, I would expect to see a build that shows innovation or skill in redstone engineering one way or another, and from what I’ve seen I don’t believe it matches up to the Engineer standards of 5 years ago, let alone today. Again, no hard feelings, I’m just sharing my honest thoughts on the build itself.

Some things I would like to see in an Engineer-level CPU of today would be:

  • Better wiring quality
  • Faster clock speed, at least 10 ticks/cycle
  • Caching
  • Unique features that make the processor stand out from other designs
1 Like
16

Minecraft name: b3nt1_xdxd (No, I don’t believe it either) , QSpry, SpryQBD, Spry0, SpryNebula, NebulaS1pry, rosneb, _Nebula__, SpryNebula53598

What’s a thing you have made which demonstrates sufficient engineering knowledge?:

NPPU3, pipelined minecraft processor /warp dasNPPU

image
image535×114 13.3 KB

Specs-

4 tick ALU, 7 dual read general purpose registers (virtual zero register), 5 stage pipeline (fetch, decode, execute, memory, writeback, ), 128 lines of program memory, 64 byte data memory,

13 ticks per clock cycle

What engineering work went into designing this device?: I was always inspired by all of the server’s engineers, who encouraged me to keep trying and tought me (through their applications) that no matter how badly they failed, they kept rebuilding and redesigning.

*This CPU was inspired by rzecz, sammyuri and Tuchi_. so much thanks to them for inspiring me in computational redstone*

I began to design the first version of the CPU, beginning with the 4 tick ALU (credit to firetner) and dual read registers. Then made a 3 bit control ROM capable of executing just 7 different instructions. For a while I lost interest in making the CPU and decided to quit and I would never apply to get engineer. I wanted this to be better than my 2 previous family members of NPPU (NPPU and GPR POD), which only had small amounts of instructions and no pipelines, and that didn’t really happen. But then I came back a month later ready to redesign the computer entirely. I kept with a 4 tick ALU and 7 general purpose registers, but redesigned the control ROM to 5 bits, much more capable at a maximum of 32 executable instructions. Then I designed the pipeline registers, program ROM with 128 lines and a RAM device of 64 bytes. Several of my parts were flawed, like I coudln’t easily get output from the ALU, and it was hard to input to it as well. I had to fix all of these, which was very annoying. I finally started creating an instruction set architechture. At that point, I had really acheived my goal of far exceeding NPPU and GPR Pod. (Exceeding them more than those computers could ever wish to be :stuck_out_tongue:)

Image/s and/or video/s of the device:

image
image1916×1042 392 KB

image
image1907×1037 231 KB

17

oops didn’t mean to do that

18

I’ve noticed in game and within the application that my computer is not sufficiently advanced for engineer, and I haven’t realized because all that the read before posting says is “knowledge about something similar level to a CPU”

19

I’ll look into drafting up a new post, I haven’t checked it out in a while

20

QSpry is a enginer?